The invention relates to a liquid crystal display (LCD) substrate, and more particularly, to a LCD substrate having spacers with steps and a fabrication method thereof using a photolithographic process.
Liquid crystal displays (LCDs) typically comprise a pair of opposing substrates and a liquid crystal layer interposed therebetween. And a plurality of photo spacers is defined the distance between the opposing substrates. (i.e., cell gap). In order to extend the category of the LCD application, the cell gap of the LCD shall be shrunk and cell gap uniformity control will be a key issue in manufacturing. An uneven cell gap may cause luminance variation over a line or a region of the LCD panel, hereinafter referred to as mura defects.
Mura defects are related to the density of photo spacers or contact areas of the substrate with photo spacers. When external force temporarily applied, such as finger wiping, the photo spacers are deformed, causing photo spacer deviation. However, as the density of the photo spacer is large, the friction force increases. The spacer deviation cannot recover even if force removed, thereby causing a wipe mura defect.
If the density of the spacers decreases to ameliorate the wipe mura defect, other problems will occur. For example, when normal force is exerted on the substrate, the spacer deforms. When the density of the photo spacer is reduced, however, the support provided thereby is insufficient to withstand the force such that deformation cannot recover even if the force is removed, resulting in a push mura defect.
U.S. Patent. No. 2002/0075443, the entity of which is fully incorporated by reference herein, Shimizu et al. disclose two different height column-shaped spacers to solve the aforementioned problems.
Two different height column-shaped spacers are formed on the color filter substrate. One spacer contacts the TFT substrate, while the other does not. FIG. 1 is a cross section illustrating two different height column-shaped spacers on the color filter substrate. A TFT substrate 100A comprises signal lines 103 and 104, an insulating layer 150, a passivation layer 108, and an alignment layer 111 thereon. A color filter substrate 100B comprises a substrate 205, a black matrix (BM) 203, a passivation layer 204, spacers 1b and 1c, and an alignment layer 208. A liquid crystal layer 900 is interposed between the TFT substrate 100A and the color filter substrate 100B.
Spacer 1b disposed on the signal line 104 contacts the TFT substrate 100A, thereby creating a specific gap between the TFT substrate 100A and the color filter substrate 100B. The spacer 1c is not disposed on the signal line 104 and often kept a small distance away from the TFT substrate 100A. When a normal force is applied on the LCD substrate, the spacer 1b can be elastically deformed while the spacer 1c can contact the TFT substrate 100A. The entire density of the spacer increases such that more load can be sustained, thereby preventing push mura defects.
FIG. 2 is a cross section illustrating another embodiment of two different height column-shaped spacers according to U.S. Patent. No. 2002/0075443. Only a portion of the color filter substrate 100B is shown for the sake of simplicity. Numeral 205 denotes a substrate, 202 denotes a color filter, 203 denotes a black matrix (BM), 204 denotes a passivation layer, and 311 denotes a base pattern. The spacer 1b is disposed on the base pattern 311. Similarly, the spacer 1b contacts the TFT substrate (not shown), while the spacer 1c is kept a small distance from the TFT substrate. When a normal force is applied on the LCD substrate, the spacer 1b can be elastically deformed while the spacer 1c can contact the TFT substrate. The entire density of the spacer increases such that more load can be sustained, thereby preventing push mura defects.
Shimizu et al. also disclose a spacer with a step on top of the spacers capable of preventing push mura defects. A spacer with a step is formed on the color filter substrate. The step on the spacer partially contacts the TFT substrate. FIGS. 3a-3c schematically depict procedures for manufacturing the spacer with a step. Referring FIG. 3a, a black matrix 203 and a color filter 202 are sequentially formed on the substrate 205. A passivation layer 204 is formed on the substrate 205 covering the black matrix 203 and the color filter 202. A photoresist layer 410 is formed on the passivation layer 204.
Referring to FIG. 3b, the photoresist layer is lithographically exposed using a half-tone mask 510. The center region 413 is exposed to a higher dosage than the peripheral region 411, thus forming a spacer 420 with a step comprising a protrusion 425 and a recess 426, as shown in FIG. 3c. 
FIGS. 4a-4c schematically depict other procedures for manufacturing the spacer with a step using dual exposure steps. Referring FIG. 4a, a black matrix 203 and a color filter 202 are sequentially formed on the substrate 205. A passivation layer 204 is formed on the substrate 205 covering the black matrix 203 and the color filter 202. A photoresist layer 410 is formed on the passivation layer 204. A portion 415 of the photoresist layer 410 is exposed using a mask 510.
Referring to FIG. 4b, the photoresist layer 410 is then exposed using a second mask 510b with a smaller exposed region such that a portion 417 of the photoresist layer 410 is shielded. The region 415 is exposed to a higher dosage than the region 417, thus forming a spacer 420 with a step comprising a protrusion 425 and a recess 426, as shown in FIG. 4c. 
According to the spacers with a step as disclosed in both FIGS. 3a-3c and FIGS. 4a-4c, the protrusion 425 contacts the TFT substrate, while the recess 426 does not. When a normal force is applied on the LCD substrate, the protrusion 425 can be elastically deformed while the recess 426 can contact the TFT substrate. The entire density of the spacer increases such that more load can be sustained, thereby preventing push mura defects.
The conventional methods of forming spacers with a step require half-tone exposure or dual exposure steps, thereby creating technical hurdles, process complexity, and cost barriers.